VLAN dual-tagging QinQ Configuration – Official Technical Overview & Hardware Datasheet

PRODUCT IDENTIFICATION

The XR-Series QinQ Acceleration Engine is a dedicated hardware module and software-defined feature set designed for carrier-grade Metro Ethernet Networks (MEN). This document specifies the implementation of IEEE 802.1ad (Provider Bridges) for VLAN dual-tagging, also referred to as QinQ (802.1Q-in-802.1Q). The solution enables service providers to encapsulate customer VLAN tags (C-TAGs) within a single service-provider VLAN tag (S-TAG), thereby preserving the customer’s internal VLAN structure while maintaining massive scalability across the core network. Hardware variants include the QINQ-400G Line Card for the XR-Core chassis and the compact Edge-Mini QinQ aggregation switch.

SYSTEM HARDWARE TOPOLOGY

The QinQ encapsulation and decapsulation process is offloaded entirely to a programmable ASIC (Application-Specific Integrated Circuit), model FPA-8765, operating in cut-through mode to guarantee sub-microsecond latency. The data plane architecture supports both symmetric (outer tag push + pop) and asymmetric modes. From a physical topology perspective, the Customer Edge (CE) connects to the Network Interface Device (NID) port. The QinQ-capable Provider Edge (PE) switch adds the S-TAG based on the ingress port, VLAN ID, or a classifier rule. Egress filtering strips the S-TAG before forwarding to a downstream CE, or maintains dual tags for provider backbone bridging (PBB). The backplane of the XR-Core chassis distributes QinQ processing via a 12.8 Tbps non-blocking fabric to each line card.

DATA & CONTROL PLANE CAPABILITIES

Control plane integration relies on an extended MIB (Management Information Base) that supports dynamic QinQ VLAN Registration Protocol (QVRP) and static VLAN mapping tables. The hardware supports up to 4,096 active S-VLANs per physical port, with each S-VLAN capable of mapping up to 4,094 unique C-VLANs (resulting in a theoretical maximum of 16 million service instances). The system automatically rewrites the EtherType from 0x8100 (C-TAG) to 0x88A8 (S-TAG) on ingress and reverses the operation on egress. For double-tagged frames exceeding the standard MTU of 1518 bytes, the hardware enables an oversized MTU up to 2000 bytes on all GbE and 10GbE interfaces. Jumbo frame support (up to 9216 bytes) is available on 25/100GbE uplinks.

COMPONENT BREAKDOWN

– QinQ Tunnel Termination Module: Integrated within the FPA-8765 ASIC, supports TPID (Tag Protocol Identifier) customization (0x8100, 0x88A8, or 0x9100).
– VLAN Translation Table: 128K entry TCAM (Ternary Content-Addressable Memory) enabling 1:1, N:1, and 1:N VLAN mapping at line rate.
– Ingress Filter Processor: Performs SP (Service Provider) priority mapping based on the PCP (Priority Code Point) bits of the C-TAG to the S-TAG.
– Egress Rewrite Engine: Removes the outer S-TAG and optionally restores the original C-TAG EtherType.

OPERATIONAL SPECS MATRIX

Maximum QinQ Tunnels: 16,000 per system (XR-Core) / 1,000 per system (Edge-Mini)
Encapsulation Latency: Parameter Specification

Form Factor Modular Line Card (XR-Core) / 1RU Standalone (Edge-Mini) Switching Capacity 3.2 Tbps (XR-Core) / 56 Gbps (Edge-Mini) Power Supply 1+1 Redundant AC/DC (field-replaceable) Supported Interfaces 48x10GbE SFP+ or 4x100GbE QSFP28 (Line Card) / 8x1GbE RJ45 + 2x10GbE SFP+ (Edge-Mini) Forwarding Rate 2.4 Bpps (billion packets per second) QinQ VLAN Scale 16,000 S-VLANs, 16M sessions max Operating Temperature 0°C to 50°C (fan-cooled, 5+1 redundancy) MTBF 285,000 hours (Telcordia SR-332)

REGULATORY COMPLIANCE

– IEEE 802.1ad-2005 (Provider Bridges)
– IEEE 802.1Q-2018 (VLAN standard, including QinQ extensions)
– MEF 6.2 (Ethernet Services Definitions Phase 3)
– MEF 10.3 (EVC performance attributes)
– RoHS 2011/65/EU
– ETSI EN 300 386 V1.6.1 (EMC for Telecom)
– CE, FCC Part 15 Class A, VCCI